1. Field of the Invention
This invention relates to silicon on insulator (SOI) CMOS devices and, more specifically, to a process of forming buried contacts for both N and P channel SOI-CMOS devices using a single N+ polycrystalline silicon layer and the device.
2. Description of the Prior Art
In the manufacture of very large scale integrated circuits (VLSI), a high component packing density must be achieved. At VLSI levels, the packing density is a function of the number of levels of interconnect in the device. In addition to the aluminum level, at least one more buried level of interconnect must be achieved. Preferably, this level should have the capability of contacting source, drain and gate of both P and N channel devices in a CMOS device producing process. Further the additional level should be provided with only a minimum number of extra processing steps, since additional processing steps add to processing cost and result in reduced yields.
It is known that a layer of, for example, N+ doped polycrystalline silicon can be used as a gate material for both N channel and P channel CMOS devices. Since the polycrystalline silicon layer is normally N+ doped, it becomes relatively easy to make buried contacts to N channel devices where the source and drain are N+ doped. However, it is not a simple operation to also make such a buried contact to a P-channel device.
The prior art has noted schemes for realizing a buried contact interconnect level. These schemes utilize, for example, N+ and P+ polycrystalline silicon layers covered with a silicide. Such schemes realize fully functional interconnect levels. However, these prior art schemes suffer the drawback that they require both N+ and P+ type polycrystalline silicon layers which inherently require complex processing techniques.